IOU_TAPDLY_BYPASS (IOU_SLCR) Register Description
| Register Name | IOU_TAPDLY_BYPASS |
|---|---|
| Offset Address | 0x0000000390 |
| Absolute Address | 0x00FF180390 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000007 |
| Description | Tap Delay enables for the LQSPI and NAND controllers. |
IOU_TAPDLY_BYPASS (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| LQSPI_RX | 2 | rwNormal read/write | 0x1 | LQSPI Tap Delay Enable on Rx Clock signal. 0: enable. 1: disable (bypass tap delay). |
| NAND_DQS_OUT | 1 | rwNormal read/write | 0x1 | NAND Tap Delay Enable on DQS Output signal. 0: enable. 1: disable (bypass tap delay). |
| NAND_DQS_IN | 0 | rwNormal read/write | 0x1 | NAND Tap Delay Enable on DQS Input signal. 0: enable. 1: disable (bypass tap delay). |