DRAMTMG11 (DDRC) Register Description
| Register Name | DRAMTMG11 |
|---|---|
| Offset Address | 0x000000012C |
| Absolute Address | 0x00FD07012C (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x440C021C |
| Description | SDRAM Timing Register 11 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG11 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| post_mpsm_gap_x32 | 30:24 | rwNormal read/write | 0x44 | tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For DDR4 designs, program this to (tXMPDLL/2) and round it up to the next integer value. Unit: Multiples of 32 clocks. |
| t_mpx_lh | 20:16 | rwNormal read/write | 0xC | tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For DDR4 designs, program this to RoundUp(tMPX_LH/2)+1. Unit: clocks. |
| t_mpx_s | 9:8 | rwNormal read/write | 0x2 | tMPX_S: Minimum time CS setup time to CKE. For DDR4 designs, program this to (tMPX_S/2) and round it up to the next integer value. Unit: Clocks. |
| t_ckmpe | 4:0 | rwNormal read/write | 0x1C | DDR4: tCKMPE: Minimum valid clock requirement after MPSM entry. Unit: Clocks. Divide the value calculated using the above equation by 2, and round it up to next integer. |