PMEVTYPER8 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

PMEVTYPER8 (SMMU500) Register Description

Register Name	PMEVTYPER8
Offset Address	0x0000003420
Absolute Address	0x00FD803420 (SMMU_GPV)
Width	32
Type	rwNormal read/write
Reset Value	0x00000000
Description	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter

PMEVTYPER8 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
P	31	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
U	30	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSP	29	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSU	28	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EVENT	4:0	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details