L3_TM_DIG_6 (SERDES) Register Description
| Register Name | L3_TM_DIG_6 |
|---|---|
| Offset Address | 0x000000D06C |
| Absolute Address | 0x00FD40D06C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_TM_DIG_6 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_DIG_6_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| Reserved | 7 | roRead-only | 0x0 | Value generated by PCW. |
| force_bypass_on_err | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| suppress_err | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bypass_OHC | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bypass_decoder | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_bypass_dec | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bypass_descram | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_bypass_descram | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |