GICP1_IRQ_STATUS (LPD_SLCR) Register - GICP1_IRQ_STATUS (LPD_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

GICP1_IRQ_STATUS (LPD_SLCR) Register Description

Register NameGICP1_IRQ_STATUS
Offset Address0x0000008014
Absolute Address 0x00FF418014 (LPD_SLCR)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

GICP1_IRQ_STATUS (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src3131wtcReadable, write a 1 to clear0x0Gigabit Ethernet3 interrupt
src3030wtcReadable, write a 1 to clear0x0Gigabit Ethernet2 wakeup interrupt
src2929wtcReadable, write a 1 to clear0x0Gigabit Ethernet2 interrupt
src2828wtcReadable, write a 1 to clear0x0Gigabit Ethernet1 wakeup interrupt
src2727wtcReadable, write a 1 to clear0x0Gigabit Ethernet1 interrupt
src2626wtcReadable, write a 1 to clear0x0Ethernet0 wakeup interrupt
src2525wtcReadable, write a 1 to clear0x0Ethernet0 interrupt
src2424wtcReadable, write a 1 to clear0x0AMS interrupt
src2323wtcReadable, write a 1 to clear0x0AIB AXI interrupt
src2222wtcReadable, write a 1 to clear0x0ATB interrupt
src2121wtcReadable, write a 1 to clear0x0WDT in the CSUPMU: This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src2020wtcReadable, write a 1 to clear0x0WDT in the LPD (IOU). This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src1919wtcReadable, write a 1 to clear0x0SDIO1 wake interrupt
src1818wtcReadable, write a 1 to clear0x0SDIO0 wake interrupt
src1717wtcReadable, write a 1 to clear0x0SDIO1 interrupt
src1616wtcReadable, write a 1 to clear0x0SDIO0 interrupt
src1515wtcReadable, write a 1 to clear0x0Triple Time Counter3
src1414wtcReadable, write a 1 to clear0x0Triple Time Counter3
src1313wtcReadable, write a 1 to clear0x0Triple Time Counter3
src1212wtcReadable, write a 1 to clear0x0Triple Timer Counter2
src1111wtcReadable, write a 1 to clear0x0Triple Timer Counter2
src1010wtcReadable, write a 1 to clear0x0Triple Timer Counter2
src9 9wtcReadable, write a 1 to clear0x0Triple Timer counter1
src8 8wtcReadable, write a 1 to clear0x0Triple Timer counter1
src7 7wtcReadable, write a 1 to clear0x0Triple Timer counter1
src6 6wtcReadable, write a 1 to clear0x0Triple Timer counter0
src5 5wtcReadable, write a 1 to clear0x0Triple Timer counter0
src4 4wtcReadable, write a 1 to clear0x0Triple Timer counter0
src3 3wtcReadable, write a 1 to clear0x0APU_IPI0: OR of all of IPIs targeted to APU CPU
src2 2wtcReadable, write a 1 to clear0x0RPU_IPI1: OR of all of IPIs targeted to RPU CPU1
src1 1wtcReadable, write a 1 to clear0x0RPU_IPI0: OR of all of IPIs targeted to RPU CPU0
src0 0wtcReadable, write a 1 to clear0x0PL_IPI3: OR of all of IPIs targeted to RPU PL3