Chnl_int_sts (UART) Register Description
| Register Name | Chnl_int_sts |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address |
0x00FF000014 (UART0) 0x00FF010014 (UART1) |
| Width | 32 |
| Type | wtcReadable, write a 1 to clear |
| Reset Value | 0x00000200 |
| Description | Channel Interrupt Status Register |
The Channel Interrupt Status register indicates any interrupt events that have occurred since this register was last cleared. The bits in this register are compared with the interrupt mask and used to assert the interrupt output. This register indicated the unmasked status, allowing software to implement a polling method of interrupt handling.
Chnl_int_sts (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:14 | wtcReadable, write a 1 to clear | 0x0 | Reserved, read as zero, ignored on write. |
| RBRK | 13 | wtcReadable, write a 1 to clear | 0x0 | Receiver break detect interrupt status: This event is triggered whenever the receiver detects ua_rxd low for more than a full frame (start + data + parity + stop). 0: no interrupt occurred 1: interrupt occurred |
| TOVR | 12 | wtcReadable, write a 1 to clear | 0x0 | Transmitter FIFO Overflow interrupt mask status: This event is triggered whenever a new word is pushed into the transmit FIFO when there is not enough room for all of the data. This will be set as a result of any write when the TFUL flag in Channel_sts_reg0 is already set, or a double byte write when the TNFUL flag in Channel_sts_reg0 is already set. 0: no interrupt occurred 1: interrupt occurred |
| TNFUL | 11 | wtcReadable, write a 1 to clear | 0x0 | Transmitter FIFO Nearly Full interrupt mask status: This event is triggered whenever a new word is pushed into the transmit FIFO causing the fill level to be such that there is not enough space for a further write of the number of bytes currently specified in the WSIZE bits in the Mode register. If this further write were currently attempted it would cause an overflow. Note that when WSIZE is 00, this assumes that a two byte write would be attempted and hence a single byte write is still possible without overflow by driving byte_sel low for the write. 0: no interrupt occurred 1: interrupt occurred |
| TTRIG | 10 | wtcReadable, write a 1 to clear | 0x0 | Transmitter FIFO Trigger continuous status 0: 0: Tx FIFO fill level is less than TTRIG 1:Tx FIFO fill level is greater than or equal to TTRIG. |
| DMSI | 9 | wtcReadable, write a 1 to clear | 0x1 | Delta Modem Status Indicator interrupt mask status: This event is triggered whenever the DCTS, DDSR, TERI, or DDCD in the modem status register are being set. 0: no interrupt occurred 1: interrupt occurred |
| TIMEOUT | 8 | wtcReadable, write a 1 to clear | 0x0 | Receiver Timeout Error interrupt mask status: This event is triggered whenever the receiver timeout counter has expired due to a long idle condition. 0: no interrupt occurred 1: interrupt occurred |
| PARE | 7 | wtcReadable, write a 1 to clear | 0x0 | Receiver Parity Error interrupt mask status: This event is triggered whenever the received parity bit does not match the expected value. 0: no interrupt occurred 1: interrupt occurred |
| FRAME | 6 | wtcReadable, write a 1 to clear | 0x0 | Receiver Framing Error interrupt mask status: This event is triggered whenever the receiver fails to detect a valid stop bit. 0: no interrupt occurred 1: interrupt occurred |
| ROVR | 5 | wtcReadable, write a 1 to clear | 0x0 | Receiver Overflow Error interrupt mask status: This event is triggered whenever the contents of the receiver shift register have not yet been transferred to the receiver FIFO and a new start bit is detected. This may be due to the FIFO being full, or due to excessive clock boundary delays. 0: no interrupt occurred 1: interrupt occurred |
| TFUL | 4 | wtcReadable, write a 1 to clear | 0x0 | Transmitter FIFO Full interrupt mask status: This event is triggered whenever a new word is inserted into the transmit FIFO causing it to go from a non-full condition to a full condition. 0: no interrupt occurred 1: interrupt occurred |
| TEMPTY | 3 | wtcReadable, write a 1 to clear | 0x0 | Transmitter FIFO Empty interrupt mask status: This event is triggered whenever the final word is removed from the transmit FIFO. 0: no interrupt occurred 1: interrupt occurred |
| RFUL | 2 | wtcReadable, write a 1 to clear | 0x0 | Receiver FIFO Full interrupt mask status: This event is triggered whenever a new word is inserted into the receive FIFO causing it to go from a non-full condition to a full condition. 0: no interrupt occurred 1: interrupt occurred |
| REMPTY | 1 | wtcReadable, write a 1 to clear | 0x0 | Receiver FIFO Empty interrupt mask status: This event is triggered upon exit of the final word from the receive FIFO. 0: no interrupt occurred 1: interrupt occurred |
| RTRIG | 0 | wtcReadable, write a 1 to clear | 0x0 | Receiver FIFO Trigger interrupt mask status: This event is triggered whenever a new word is inserted into the receive FIFO. 0: no interrupt occurred 1: interrupt occurred |