ATTR_97 (PCIE_ATTRIB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ATTR_97 (PCIE_ATTRIB) Register Description

Register NameATTR_97
Offset Address0x0000000184
Absolute Address 0x00FD480184 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000104
DescriptionATTR_97

This register should only be written to during reset of the PCIe block

ATTR_97 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_ltssm_max_link_width11:6rwNormal read/write0x4Used by LTSSM to set Maximum Link Width.
Valid settings are:
000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].
attr_link_cap_max_link_width 5:0rwNormal read/write0x4Maximum Link Width.
Valid settings are:
000001b x1, 000010b x2, 000100b x4, 001000b x8.