RPU_0_SLV_BASE (RPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RPU_0_SLV_BASE (RPU) Register Description

Register NameRPU_0_SLV_BASE
Offset Address0x0000000124
Absolute Address 0x00FF9A0124 (RPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSlave Base Address Register

RPU_0_SLV_BASE (RPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
ADDR 7:0rwNormal read/write0x0Slave address is appended wih 8 bits to generate 23 bit address.
If incomign access is going to caches, RPU use this register to generate final address passed to R5
{RPU_0_SLV_BASE_ADDR[7:0], ARADDR[14:0]}