DSTS (USB3_XHCI) Register Description
| Register Name | DSTS |
|---|---|
| Offset Address | 0x000000C70C |
| Absolute Address |
0x00FE20C70C (USB3_0_XHCI) 0x00FE30C70C (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled, RSS and SSS fields always return 0 when read. |
DSTS (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | roRead-only | 0x0 | Reserved |
| DCNRD | 29 | roRead-only | 0 | Device Controller Not Ready The bit indicates that the core is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions, it takes 256 bus clock cycles from the time DCTL[31].Run/Stop is set. During hibernation, if the UTMI/ULPI PHY is in suspended state, then the 256-bus clock cycle delay starts after the PHY exited suspended state. Software must set DCTL[31].Run/Stop to 1 and wait for this bit to be de-asserted to zero before processing DSTS.USBLnkSt. This bit is valid only when DWC_USB3_EN_PWROPT is set to 2 and GCTL[1].GblHibernationEn =1. |
| SRE | 28 | wtcReadable, write a 1 to clear | 0x0 | Save Restore Error. Currently not supported. |
| Reserved | 27:26 | roRead-only | 0x0 | Reserved |
| RSS | 25 | roRead-only | 0 | RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process, it completes the command by setting DSTS.RSS to 0. |
| SSS | 24 | roRead-only | 0 | SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process, it completes the command by setting DSTS.SSS to 0. |
| COREIDLE | 23 | roRead-only | 0 | Core Idle The bit indicates that the core finished transferring all RxFIFO data to system memory, writing out all completed descriptors, and all Event Counts are zero. Note: While testing for Reset values, mask out the read value. This bit represents the changing state of the core and does not hold a static value. |
| DEVCTRLHLT | 22 | roRead-only | 0 | Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The core sets this bit to 1 when, after SW sets Run/Stop to 0, the core is idle and the lower layer finishes the disconnect process. When Halted=1, the core does not generate Device events. Note: The core does not set this bit to 1 if GEVNTCOUNTn has some valid value. Software needs to acknowledge the events that are generated (by writing to GEVNTCOUNTn) while it is waiting for this bit to be set to 1. |
| USBLNKST | 21:18 | roRead-only | 0 | USBLNKST. USB/Link State In SS mode: LTSSM State - 4h0: U0 - 4h1: U1 - 4h2: U2 - 4h3: U3 - 4h5: RX_DET - 4h6: SS_INACT - 4h7: POLL - 4h8: RECOV - 4h9: HRESET - 4ha: CMPLY - 4hb: LPBK - 4hf: Resume/Reset In HS/FS/LS mode: - 4h0: On state - 4h2: Sleep (L1) state - 4h3: Suspend (L2) state - 4h4: Disconnected state (Default state) - 4h5: Early Suspend state (valid only when Hibernation is disabled, GCTL[1].GblHibernationEn = 0) - 4he: Reset (valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1) - 4hf: Resume (valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1) The link state Resume/Reset indicates that the core received a resume or USB reset request from the host while the link was in hibernation. Software must write 8 (Recovery) to the DCTL.ULStChngReq field to acknowledge the resume/reset request. When Hibernation is enabled, GCTL[1].GblHibernationEn = 1, this field USBLnkSt is valid only when DCTL[31].Run/Stop set to 1 and DSTS[29].DCNRD = 0. Note: If SSIC is enabled, while exiting a low power state, the USBLnkSt field indicates Resume/Reset even for a disconnect condition because a resume precedes the disconnect. |
| RXFIFOEMPTY | 17 | roRead-only | 0 | RxFIFO Empty. |
| SOFFN | 16:3 | roRead-only | 0 | Frame/Microframe Number of the Received SOF. When the core is operating at high-speed, - [16:6] indicates the frame number - [5:3] indicates the microframe number When the core is operating at full-speed, - [16:14] is not used. Software can ignore these 3 bits - [13:3] indicates the frame number |
| CONNECTSPD | 2:0 | roRead-only | 0 | Connected Speed (ConnectSpd) Indicates the speed at which the controller has come up after speed detection through a chirp sequence. - 3b100: SuperSpeed (PHY clock is running at 125 or 250 MHz) - 3b000: High-speed (PHY clock is running at 30 or 60 MHz) - 3b001: Full-speed (PHY clock is running at 30 or 60 MHz) - 3b010: Low-speed (PHY clock is running at 6 MHz) - 3b011: Full-speed (PHY clock is running at 48 MHz) Low-speed is not supported for devices using a UTMI+ PHY. |