SMMU_CB3_TLBIIPAS2L_high (SMMU500) Register Description
| Register Name | SMMU_CB3_TLBIIPAS2L_high |
|---|---|
| Offset Address | 0x000001363C |
| Absolute Address | 0x00FD81363C (SMMU_GPV) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup |
SMMU_CB3_TLBIIPAS2L_high (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Address | 3:0 | woWrite-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |