SMMU_CB1_TLBIVAA_high (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB1_TLBIVAA_high (SMMU500) Register Description

Register NameSMMU_CB1_TLBIVAA_high
Offset Address0x000001160C
Absolute Address 0x00FD81160C (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.

SMMU_CB1_TLBIVAA_high (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ASID31:16woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Address 4:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details