L2_PLL_SS_STEP_SIZE_1 (SERDES) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

L2_PLL_SS_STEP_SIZE_1 (SERDES) Register Description

Register NameL2_PLL_SS_STEP_SIZE_1
Offset Address0x000000A374
Absolute Address 0x00FD40A374 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L2_PLL_SS_STEP_SIZE_1 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PLL_SS_STEP_SIZE_1_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ss_step_size_1 7:0rwNormal read/write0x0Value generated by PCW.