DP_TX_AUDIO_CONTROL (DISPLAY_PORT) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

DP_TX_AUDIO_CONTROL (DISPLAY_PORT) Register Description

Register NameDP_TX_AUDIO_CONTROL
Offset Address0x0000000300
Absolute Address 0x00FD4A0300 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEnables audio stream packets in main link and provides buffer control.

DP_TX_AUDIO_CONTROL (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4razRead as zero0x0
Reserved 3:1rwNormal read/write0x0
TX_AUD_CTRL 0rwNormal read/write0x0Audio Enable