DP_LINK_QUAL_PATTERN_SET (DISPLAY_PORT) Register Description
| Register Name | DP_LINK_QUAL_PATTERN_SET |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00FD4A0010 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | To transmit the link quality pattern |
DP_LINK_QUAL_PATTERN_SET (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0x0 | |
| EXT | 2 | rwNormal read/write | 0x0 | This bit is used along with LINK_QUAL_PAT_SET. Set this bit to 1 to transmit HBR2 Compliance pattern(when LINK_QUAL_PAT_SET = 2b01) or 80-bit custom pattern(when LINK_QUAL_PAT_SET = 2b00). |
| LNK_QUAL_PAT_SET | 1:0 | rwNormal read/write | 0x0 | Transmit the link quality pattern. - [1:0] - Enable transmission of the link quality test patterns. o 00 = Link quality test pattern not transmitted o 01 = D10.2 test pattern (unscrambled) transmitted(Reserved. This feature can be enabled using TP1 selection) o 10 = Symbol Error Rate measurement pattern o 11 = PRBS7 transmitted (Reserved. This feature can be enabled using PRBS7 transmit feature Reg 0x230) |