MIO_PIN_30 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

MIO_PIN_30 (IOU_SLCR) Register Description

Register NameMIO_PIN_30
Offset Address0x0000000078
Absolute Address 0x00FF180078 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 30 Multiplexer Controls.

MIO_PIN_30 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [30] input/output bank 1.
1: CAN0 RX input.
2: I2C0 SCL input/output clock.
3: LPD SWDT clock output.
4: SPI0 MISO input/output.
5: TTC0 clock input.
6: UART0 RxD input.
7: TracePort DQ[8] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: PMU GPI1 [14] input.
2: Scan Test [30] input/output.
3: DisplayPort Aux Data input.
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: PCIe Reset input.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM0 RGMII Tx Data [3] output.
Reserved 0rwNormal read/write0x0reserved