DDRC_MRR_DATA0 (DDR_QOS_CTRL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

DDRC_MRR_DATA0 (DDR_QOS_CTRL) Register Description

Register NameDDRC_MRR_DATA0
Offset Address0x000000051C
Absolute Address 0x00FD09051C (DDR_QOS_CTRL)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDDRC MRR Register Data

DDRC_MRR_DATA0 (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LSB31:0roRead-only0x0DDRC MRR Register LSB Data