PP1_LAST_TILE_POS_END (GPU) Register Description
| Register Name | PP1_LAST_TILE_POS_END |
|---|---|
| Offset Address | 0x000000B014 |
| Absolute Address | 0x00FD4BB014 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Last Tile Where Processing Completed Register |
PP1_LAST_TILE_POS_END (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | rwNormal read/write | 0x0 | Read undefined. |
| TILEY_END | 23:16 | rwNormal read/write | 0x0 | The y position of the last tile that processing has ended, that is written back. Note: Scaling is equal to that of the Begin New Tile command 15 in the polygon list. |
| Reserved | 15:8 | rwNormal read/write | 0x0 | Read undefined. |
| TILEX_END | 7:0 | rwNormal read/write | 0x0 | The x position of the last tile that processing has ended, that is written back. Note: Scaling is equal to that of the Begin New Tile command 15 in the polygon list. |