| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:15 | rwNormal read/write | 0x0 | reserved |
| tbu_TBU5_5_cg | 14 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU5_5 |
| tbu_TBU5_5_pd | 13 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU5_5 |
| tbu_TBU4_4_cg | 12 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU4_4 |
| tbu_TBU4_4_pd | 11 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU4_4 |
| tbu_TBU3_3_cg | 10 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU3_3 |
| tbu_TBU3_3_pd | 9 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU3_3 |
| pd_mst_br_TBU2_2 | 8 | rwNormal read/write | 0x1 | Power down request signal for TBU Bridge Master TBU2_2 |
| pd_slv_br_TBU2_2 | 7 | rwNormal read/write | 0x1 | Power down request signal for TBU Bridge Slave TBU2_2 |
| tbu_TBU2_2_cg | 6 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU2_2 |
| tbu_TBU2_2_pd | 5 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU2_2 |
| tbu_TBU1_1_cg | 4 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU1_1 |
| tbu_TBU1_1_pd | 3 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU1_1 |
| tbu_TBU0_0_cg | 2 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU0_0 |
| tbu_TBU0_0_pd | 1 | rwNormal read/write | 0x1 | Low power entry request signal for TBU TBU0_0 |
| tcu | 0 | rwNormal read/write | 0x1 | Low power entry request signal for TCU |