GDBGFIFOSPACE (USB3_XHCI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GDBGFIFOSPACE (USB3_XHCI) Register Description

Register NameGDBGFIFOSPACE
Offset Address0x000000C160
Absolute Address 0x00FE20C160 (USB3_0_XHCI)
0x00FE30C160 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00420000
DescriptionGlobal Debug Queue/FIFO Space Available Register
Bit Bash test should not be done on this debug register.

GDBGFIFOSPACE (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SPACE_AVAILABLE31:16roRead-only0x42SPACE_AVAILABLE
Reserved15:9roRead-only0x0Reserved
FIFO_QUEUE_SELECT 8:0rwNormal read/write0x0FIFO/Queue Select (or) Port-Select
- FIFO/Queue Select[8:5] indicates the FIFO/Queue Type
- FIFO/Queue Select[4:0] indicates the FIFO/Queue Number
For example, 9b0_0010_0001 refers to RxFIFO_1 and 9b0_0101_1110 refers to TxReqQ_30.
- 9b0_0001_1111 to 9b0_0000_0000: TxFIFO_31 to TxFIFO_0
- 9b0_0011_1111 to 9b0_0010_0000: RxFIFO_31 to RxFIFO_0
- 9b0_0101_1111 to 9b0_0100_0000: TxReqQ_31 to TxReqQ_0
- 9b0_0111_1111 to 9b0_0110_0000: RxReqQ_31 to RxReqQ_0
- 9b0_1001_1111 to 9b0_1000_0000: RxInfoQ_31 to RxInfoQ_0
- 9b0_1010_0000: DescFetchQ_0 (for backwards compatibility)
- 9b0_1010_0001: EventQ_0 (for backwards compatibility)
- 9b0_1010_0010: ProtocolStatusQ_0
- 9b0_1101_1111 to 9b0_1110_0000: DescFetchQ_31 to DescFetchQ_0
- 9b0_1111_1111 to 9b0_1110_0000: WriteBack/EventQ_31 to WriteBack/EventQ_0
- 9b1_0000_0111 to 9b1_0000_0000: AuxEventQ_7 to AuxEventQ_0 (if EN_SEPARATE_DESC_QUEUES=1)
Port-Select[3:0] selects the port-number when accessing GDBGLTSSM register.