reg_errorintrsigena (SDIO) Register Description
| Register Name | reg_errorintrsigena |
|---|---|
| Offset Address | 0x000000003A |
| Absolute Address |
0x00FF16003A (SD0) 0x00FF17003A (SD1) |
| Width | 16 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Error-type Interrupts Signal Enables. |
0: masked. 1: enabled.
reg_errorintrsigena (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| errorintrsig_enableregbit12 | 12 | roRead-only | 0x0 | Bit 12. |
| errorintrsig_enableregbit10 | 10 | rwNormal read/write | 0x0 | Bit 10. |
| errorintrsig_enableregbit9 | 9 | rwNormal read/write | 0x0 | Bit 9. |
| errorintrsig_enableregbit8 | 8 | rwNormal read/write | 0x0 | Bit 8. |
| errorintrsig_enableregbit7 | 7 | rwNormal read/write | 0x0 | Bit 7. |
| errorintrsig_enableregbit6 | 6 | rwNormal read/write | 0x0 | Bit 6. |
| errorintrsig_enableregbit5 | 5 | rwNormal read/write | 0x0 | Bit 5. |
| errorintrsig_enableregbit4 | 4 | rwNormal read/write | 0x0 | Bit 4. |
| errorintrsig_enableregbit3 | 3 | rwNormal read/write | 0x0 | Bit 3. |
| errorintrsig_enableregbit2 | 2 | rwNormal read/write | 0x0 | Bit 2. |
| errorintrsig_enableregbit1 | 1 | rwNormal read/write | 0x0 | Bit 1. |
| errorintrsig_enableregbit0 | 0 | rwNormal read/write | 0x0 | Bit 0. |