QSPIDMA_DST_SIZE (QSPI) Register Description
| Register Name | QSPIDMA_DST_SIZE |
|---|---|
| Offset Address | 0x0000000804 |
| Absolute Address | 0x00FF0F0804 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DMA transfer payload |
For DMA stream-to-memory data transfer.
QSPIDMA_DST_SIZE (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| SIZE | 28:2 | woWrite-only | 0x0 | Specifies the number of 4-byte words the DMA will transfer from stream to memory Size is word aligned, so this field is only 27-bits. (2 lsbs are 0) The action of writing to this register starts a DMA transfer of length SIZE, moving data from the stream interface to ADDR. In this case, it indicates the total payload that the DMA will move from stream to memory. Note: Change this value only when controller is not communicating with the memory device. |
| Reserved | 1:0 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |