PWR_STATE (PMU_GLOBAL) Register Description
| Register Name | PWR_STATE |
|---|---|
| Offset Address | 0x0000000100 |
| Absolute Address | 0x00FFD80100 (PMU_GLOBAL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00FFFCBF |
| Description | Power State Status; PS Islands, PL Internal and FPD. |
This register provides status for two power domains and 19 power islands. The status of the 19 power islands are based on the state of the internal power control circuits. 0: powered-down. 1: powered-up. The status of the two power domains are based on the state of the isolation wall for the system signals between the LPD and the other two power domains. Note: the register retains its value during a system reset; register is reset only by a POR reset. Read-only.
PWR_STATE (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | roRead-only | 0x0 | reserved |
| PL | 23 | roRead-only | 0x1 | PL Power Domain (PLPD) status. 0: powered-down or isolated (PMU_LOCAL.DOMAIN_ISO_CTRL [PL_LP_ISO_1] = 1; this refers to the non-PCAP interface between the LPD and the PLPD). 1: powered-up and accessible. The PL power is usually controlled by an external FET via an MIO pin. |
| FP | 22 | roRead-only | 0x1 | Full-power Domain (FPD) status. 0: powered-down or isolated (PMU_LOCAL.DOMAIN_ISO_CTRL [LP_FP_ISO_2] = 1). 1: powered-up and accessible. Note: If PMU_LOCAL.DOMAIN_ISO_CTRL [LP_FP_ISO_2] = 1, then the [FP] bit will = 0, but the FPD power supply may in-fact be powered up and the system accessible for debug. When the FPD is in locked isolation (PMU_LOCAL.DOMAIN_ISO_CTRL [FP_LOCKED] = 1), the [FP] bit will be cleared because [LP_FP_ISO_2] becomes inactive in order to allow clocks and resets to enter the FPD. Thus, this field cannot be used to determine FPD accessibility in the event the FPD is locked out. The PMU_LOCAL register set is only accessible by the PMU processor. Note: To request changes to the VCC_PSINTFP power supply, refer to the REQ_PWR{UP,DWN}_TRIG registers. Note: To determine the state of the VCC_PSINTFP power supply, refer to the PMU_GLOCAL.PWR_SUPPLY_STATUS [VCC_PSINTFP] bit. |
| USB1 | 21 | roRead-only | 0x1 | USB Controller 1 power island. 0: powered-down. 1: powered-up. |
| USB0 | 20 | roRead-only | 0x1 | USB Controller 0 power island. |
| OCM_Bank3 | 19 | roRead-only | 0x1 | OCM bank 3 power island. |
| OCM_Bank2 | 18 | roRead-only | 0x1 | OCM bank 2 power island. |
| OCM_Bank1 | 17 | roRead-only | 0x1 | OCM bank 1 power island. |
| OCM_Bank0 | 16 | roRead-only | 0x1 | OCM bank 0 power island. |
| TCM1B | 15 | roRead-only | 0x1 | RPU1 TCM_B power island. |
| TCM1A | 14 | roRead-only | 0x1 | RPU1 TCM_A power island. |
| TCM0B | 13 | roRead-only | 0x1 | RPU0 TCM_B power island. |
| TCM0A | 12 | roRead-only | 0x1 | RPU0 TCM_A power island. |
| R5_1 | 11 | roRead-only | 0x1 | RPU1 power island. |
| R5_0 | 10 | roRead-only | 0x1 | RPU0 power island. |
| Reserved | 9 | roRead-only | 0x0 | reserved |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| L2_Bank0 | 7 | roRead-only | 0x1 | APU L2 Cache power island. |
| Reserved | 6 | roRead-only | 0x0 | reserved |
| PP1 | 5 | roRead-only | 0x1 | GPU Pixel Processor 1 power island. |
| PP0 | 4 | roRead-only | 0x1 | GPU Pixel Processor 0 power island. |
| ACPU3 | 3 | roRead-only | 0x1 | APU core 3 power island. |
| ACPU2 | 2 | roRead-only | 0x1 | APU core 2 power island. |
| ACPU1 | 1 | roRead-only | 0x1 | APU core 1 power island. |
| ACPU0 | 0 | roRead-only | 0x1 | APU core 0 power island. |