DFIUPD1 (DDRC) Register Description
| Register Name | DFIUPD1 |
|---|---|
| Offset Address | 0x00000001A4 |
| Absolute Address | 0x00FD0701A4 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DFI Update Register 1 |
This register is static. Static registers can only be written when the controller is in reset.
DFIUPD1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_t_ctrlupd_interval_min_x1024 | 23:16 | rwNormal read/write | 0x0 | This is the minimum amount of time between DDRC initiated DFI update requests (which is executed whenever the DDRC is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRC is idle. Unit: 1024 clocks |
| dfi_t_ctrlupd_interval_max_x1024 | 7:0 | rwNormal read/write | 0x0 | This is the maximum amount of time between DDRC initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 clocks |