SMMU_CB0_TLBSYNC (SMMU500) Register Description
| Register Name | SMMU_CB0_TLBSYNC |
|---|---|
| Offset Address | 0x00000107F0 |
| Absolute Address | 0x00FD8107F0 (SMMU_GPV) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank. |
SMMU_CB0_TLBSYNC (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| bits | 31:0 | woWrite-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |