| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| ctrl | 0x0000000004 | 1 | rwNormal read/write | 0x00000000 | General control register for the LP SLCR |
| isr | 0x0000000008 | 1 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register |
| imr | 0x000000000C | 1 | roRead-only | 0x00000001 | Interrupt Mask Register |
| ier | 0x0000000010 | 1 | woWrite-only | 0x00000000 | Interrupt Enable Register |
| idr | 0x0000000014 | 1 | woWrite-only | 0x00000000 | Interrupt Disable Register |
| itr | 0x0000000018 | 1 | woWrite-only | 0x00000000 | Interrupt Trigger Register |
| SAFETY_CHK0 | 0x0000000040 | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register |
| SAFETY_CHK1 | 0x0000000044 | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register |
| SAFETY_CHK2 | 0x0000000048 | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register |
| SAFETY_CHK3 | 0x000000004C | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register |
| CSUPMU_WDT_CLK_SEL | 0x0000000050 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SWDT clock source select |
| adma_cfg | 0x000000200C | 7 | roRead-only | 0x00000028 | GDMA RF2 Configuation |
| ADMA_RAM | 0x0000002010 | 16 | mixedMixed types. See bit-field details. | 0x00000000 | RAM control register |
| ERR_AIBAXI_ISR | 0x0000003000 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| ERR_AIBAXI_IMR | 0x0000003008 | 32 | roRead-only | 0x1DCF000F | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| ERR_AIBAXI_IER | 0x0000003010 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| ERR_AIBAXI_IDR | 0x0000003018 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| ERR_AIBAPB_ISR | 0x0000003020 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| ERR_AIBAPB_IMR | 0x0000003024 | 32 | roRead-only | 0x00000001 | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| ERR_AIBAPB_IER | 0x0000003028 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| ERR_AIBAPB_IDR | 0x000000302C | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| ISO_AIBAXI_REQ | 0x0000003030 | 32 | rwNormal read/write | 0x00000000 | Request to AIB to start Isolation. 1 Isolate. 0 No Isolation |
| ISO_AIBAXI_TYPE | 0x0000003038 | 32 | rwNormal read/write | 0x19CF000F | If 1 AIB sends SLVERR. If 0 AIB does not respond |
| ISO_AIBAXI_ACK | 0x0000003040 | 32 | roRead-only | 0x00000000 | If 1 AIB has Functionally Isolated Master and Slave |
| ISO_AIBAPB_REQ | 0x0000003048 | 32 | rwNormal read/write | 0x00000000 | Request to AIB to start Isolation. 1 Isolate. 0 No Isolation |
| ISO_AIBAPB_TYPE | 0x000000304C | 32 | rwNormal read/write | 0x00000001 | If 1 AIB sends SLVERR. If 0 AIB does not respond |
| ISO_AIBAPB_ACK | 0x0000003050 | 32 | roRead-only | 0x00000000 | If 1 AIB has Functionally Isolated Master and Slave |
| ERR_ATB_ISR | 0x0000006000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| ERR_ATB_IMR | 0x0000006004 | 32 | mixedMixed types. See bit-field details. | 0x00000003 | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| ERR_ATB_IER | 0x0000006008 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| ERR_ATB_IDR | 0x000000600C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| ATB_CMD_STORE_EN | 0x0000006010 | 32 | mixedMixed types. See bit-field details. | 0x00000003 | ATB Sideband Signals |
| ATB_RESP_EN | 0x0000006014 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ATB Sideband Signals |
| ATB_RESP_TYPE | 0x0000006018 | 32 | mixedMixed types. See bit-field details. | 0x00000003 | ATB Sideband Signals |
| ATB_PRESCALE | 0x0000006020 | 32 | mixedMixed types. See bit-field details. | 0x0000FFFF | ATB Sideband Signals |
| Mutex0 | 0x0000007000 | 32 | rwNormal read/write | 0x00000000 | LP Domain SLCR Mutex 0 register |
| Mutex1 | 0x0000007004 | 32 | rwNormal read/write | 0x00000000 | LP Domain SLCR Mutex 1 register |
| Mutex2 | 0x0000007008 | 32 | rwNormal read/write | 0x00000000 | LP Domain SLCR Mutex 2 register |
| Mutex3 | 0x000000700C | 32 | rwNormal read/write | 0x00000000 | LP Domain SLCR Mutex 3 register |
| GICP0_IRQ_STATUS | 0x0000008000 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | GIC Proxy Interrupt Status (1/2) |
| GICP0_IRQ_MASK | 0x0000008004 | 32 | roRead-only | 0xFFFFFF00 | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP0_IRQ_ENABLE | 0x0000008008 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP0_IRQ_DISABLE | 0x000000800C | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP0_IRQ_TRIGGER | 0x0000008010 | 32 | woWrite-only | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| GICP1_IRQ_STATUS | 0x0000008014 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| GICP1_IRQ_MASK | 0x0000008018 | 32 | roRead-only | 0xFFFFFFFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP1_IRQ_ENABLE | 0x000000801C | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP1_IRQ_DISABLE | 0x0000008020 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP1_IRQ_TRIGGER | 0x0000008024 | 32 | woWrite-only | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| GICP2_IRQ_STATUS | 0x0000008028 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| GICP2_IRQ_MASK | 0x000000802C | 32 | roRead-only | 0xFFFFFFFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP2_IRQ_ENABLE | 0x0000008030 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP2_IRQ_DISABLE | 0x0000008034 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP2_IRQ_TRIGGER | 0x0000008038 | 32 | woWrite-only | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| GICP3_IRQ_STATUS | 0x000000803C | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| GICP3_IRQ_MASK | 0x0000008040 | 32 | roRead-only | 0xFFFFFF01 | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP3_IRQ_ENABLE | 0x0000008044 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP3_IRQ_DISABLE | 0x0000008048 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP3_IRQ_TRIGGER | 0x000000804C | 32 | woWrite-only | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| GICP4_IRQ_STATUS | 0x0000008050 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| GICP4_IRQ_MASK | 0x0000008054 | 32 | roRead-only | 0x0FFFFFFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP4_IRQ_ENABLE | 0x0000008058 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP4_IRQ_DISABLE | 0x000000805C | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP4_IRQ_TRIGGER | 0x0000008060 | 32 | woWrite-only | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| GICP_PMU_IRQ_STATUS | 0x00000080A0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| GICP_PMU_IRQ_MASK | 0x00000080A4 | 32 | mixedMixed types. See bit-field details. | 0x0000001F | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| GICP_PMU_IRQ_ENABLE | 0x00000080A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| GICP_PMU_IRQ_DISABLE | 0x00000080AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| GICP_PMU_IRQ_TRIGGER | 0x00000080B0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
| afi_fs | 0x0000009000 | 16 | mixedMixed types. See bit-field details. | 0x00000200 | afi fs SLCR control register. Do not change the bits durin |
| lpd_cci | 0x000000A000 | 32 | rwNormal read/write | 0x03801C07 | CCI Configuration. This register may be written to only when FPD Interconnect is in reset. |
| lpd_cci_addrmap | 0x000000A004 | 32 | rwNormal read/write | 0x00C000FF | Address Decode for each reguion of the address map of CCI. This register may be written to only when FPD Interconnect is in reset. |
| lpd_cci_qvnprealloc | 0x000000A008 | 32 | mixedMixed types. See bit-field details. | 0x00330330 | QVN Preallocation Configuration |
| lpd_smmu | 0x000000A020 | 32 | mixedMixed types. See bit-field details. | 0x0000003F | SMMU Configuration. This register may be written to only when FPD Interconnect is in reset. |
| lpd_apu | 0x000000A040 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | APU Configuration. This register may be written to only when APU is in reset |