ATTR_110 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_110 |
|---|---|
| Offset Address | 0x00000001B8 |
| Absolute Address | 0x00FD4801B8 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0000FA84 |
| Description | ATTR_110 |
This register should only be written to during reset of the PCIe block
ATTR_110 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_rp_auto_spd_loopcnt | 15:11 | rwNormal read/write | 0x1F | number of times RP tries to negotiate for the highest Link speed possible |
| attr_rp_auto_spd | 10:9 | rwNormal read/write | 0x1 | Controls the number of times the device as Root Port tries to up speed 00 = no Link speed up-negotiation after 1st attempt 01 = Link speed up-negotiation for RP_AUTO_SPD_LOOPCNT times 10 = Link speed up-negotiation for indefinitely 11 = reserved |
| attr_trn_np_fc | 7 | rwNormal read/write | 0x1 | When true enables trn_rnp_req_n pin |
| attr_ur_inv_req | 2 | rwNormal read/write | 0x1 | When TRUE handle received ATS Invalidate request messages as unsupported request. When FALSE pass received ATS Invalidate request messages to the user |
| attr_cfg_ecrc_err_cplstat | 1:0 | rwNormal read/write | 0x0 | Controls CMM handling of received config requests with ECRC errors 00 = do not return a completion 01 = return a completion with status UR 10 = return a completion with status CRS 11 = return a completion with status CA |