SMMU_CB0_PRRR_MAIR0 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

SMMU_CB0_PRRR_MAIR0 (SMMU500) Register Description

Register Name	SMMU_CB0_PRRR_MAIR0
Offset Address	0x0000010038
Absolute Address	0x00FD810038 (SMMU_GPV)
Width	32
Type	rwNormal read/write
Reset Value	0x00000000
Description	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.

SMMU_CB0_PRRR_MAIR0 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Description
NOS7	31	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS6	30	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS5	29	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS4	28	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS3	27	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS2	26	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS1	25	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS0	24	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NS1	19	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NS0	18	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DS1	17	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DS0	16	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR7	15:14	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR6	13:12	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR5	11:10	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR4	9:8	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR3	7:6	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR2	5:4	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR1	3:2	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR0	1:0	rwNormal read/write	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details