SMMU_CB11_NMRR_MAIR1 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

SMMU_CB11_NMRR_MAIR1 (SMMU500) Register Description

Register Name	SMMU_CB11_NMRR_MAIR1
Offset Address	0x000001B03C
Absolute Address	0x00FD81B03C (SMMU_GPV)
Width	32
Type	rwNormal read/write
Reset Value	0x00000000
Description	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.

SMMU_CB11_NMRR_MAIR1 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
OR7	31:30	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR6	29:28	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR5	27:26	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR4	25:24	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR3	23:22	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR2	21:20	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR1	19:18	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OR0	17:16	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR7	15:14	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR6	13:12	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR5	11:10	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR4	9:8	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR3	7:6	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR2	5:4	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR1	3:2	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IR0	1:0	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details