Mutex3 (LPD_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Mutex3 (LPD_SLCR) Register Description

Register NameMutex3
Offset Address0x000000700C
Absolute Address 0x00FF41700C (LPD_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionLP Domain SLCR Mutex 3 register

Mutex3 (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
id31:0rwNormal read/write0x0SW mutex can be activated by any master by writing its non-zero ID value.
Mutex Status:
Availibility: When this register is zero means mutex is available for any master. After reset, this mutex is available to any master.
Activation: When this mutex is available then any master can occupied by writing non-zero value to this register. Further non-zero writes to this register will be ignored.
Deactivation/Release: Mater has to write zero to this register to release this Mutex.