Intrpt_Mask (I2C) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Intrpt_Mask (I2C) Register Description

Register NameIntrpt_Mask
Offset Address0x0000000020
Absolute Address 0x00FF020020 (I2C0)
0x00FF030020 (I2C1)
Width16
TyperoRead-only
Reset Value0x000002FF
DescriptionInterrupt Mask

Each bit in this register corresponds to a bit in the interrupt status register. If bit i in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit i in the interrupt status register is set. Bits in this register are set through a write to the interrupt disable register and are cleared through a write to the interrupt enable register. All mask bits are set and all interrupts are disabled after reset. Interrupt mask register has the same format as the interrupt status register.

Intrpt_Mask (I2C) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:10roRead-only0x0Reserved, read as zero, ignored on write.
ARB_LOST 9roRead-only0x1arbitration lost
1 = Mask this interrupt
0 = unmask this interrupt
Reserved 8roRead-only0x0Reserved, read as zero, ignored on write.
RX_UNF 7roRead-only0x1FIFO receive underflow
1 = Mask this interrupt
0 = unmask this interrupt
TX_OVF 6roRead-only0x1FIFO transmit overflow
1 = Mask this interrupt
0 = unmask this interrupt
RX_OVF 5roRead-only0x1Receive overflow
1 = Mask this interrupt
0 = unmask this interrupt
SLV_RDY 4roRead-only0x1Monitored slave ready
1 = Mask this interrupt
0 = unmask this interrupt
TO 3roRead-only0x1Transfer time out
1 = Mask this interrupt
0 = unmask this interrupt
NACK 2roRead-only0x1Transfer not acknowledged
1 = Mask this interrupt
0 = unmask this interrupt
DATA 1roRead-only0x1More data
1 = Mask this interrupt
0 = unmask this interrupt
COMP 0roRead-only0x1Transfer complete
1 = Mask this interrupt
0 = unmask this interrupt