SMMU_ITIP (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_ITIP (SMMU500) Register Description

Register NameSMMU_ITIP
Offset Address0x0000002004
Absolute Address 0x00FD802004 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionEnables the MMU-500 to read the status of the spniden signal.

SMMU_ITIP (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SPINDEN 0roRead-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details