REQ_PWRDWN_INT_MASK (PMU_GLOBAL) Register - REQ_PWRDWN_INT_MASK (PMU_GLOBAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

REQ_PWRDWN_INT_MASK (PMU_GLOBAL) Register Description

Register NameREQ_PWRDWN_INT_MASK
Offset Address0x0000000214
Absolute Address 0x00FFD80214 (PMU_GLOBAL)
Width32
TyperoRead-only
Reset Value0x00FFF4BF
DescriptionPower-down or RAM Retention Request; Interrupt Mask.

0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.

REQ_PWRDWN_INT_MASK (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0reserved
PL23roRead-only0x1Programmable Logic, PL. Controlled by external FET via MIO pin. This optional control uses MIO [32] and is equivalent to PMU signal [6].
FP22roRead-only0x1Full-power Domain, FPD. Controlled by external FET via MIO pin. This optional control uses MIO [31] and is equivalent to PMU signal [5].
USB121roRead-only0x1USB controller 1.
USB020roRead-only0x1USB controller 0.
OCM_Bank319roRead-only0x1OCM Bank 3.
OCM_Bank218roRead-only0x1OCM Bank 2.
OCM_Bank117roRead-only0x1OCM Bank 1.
OCM_Bank016roRead-only0x1OCM Bank 0.
TCM1B15roRead-only0x1RPU core 1, TCM_B.
TCM1A14roRead-only0x1RPU core 1, TCM_A.
TCM0B13roRead-only0x1RPU core 0, TCM_B.
TCM0A12roRead-only0x1RPU core 0, TCM_A.
Reserved11roRead-only0x0reserved
RPU10roRead-only0x1RPU processors.
Reserved 9roRead-only0x0reserved
Reserved 8roRead-only0x0reserved
L2_Bank0 7roRead-only0x1APU L2 Cache.
Reserved 6roRead-only0x0reserved
PP1 5roRead-only0x1GPU Pixel Processor 1.
PP0 4roRead-only0x1GPU Pixel Processor 0.
ACPU3 3roRead-only0x1APU core 3.
ACPU2 2roRead-only0x1APU core 2.
ACPU1 1roRead-only0x1APU core 1.
ACPU0 0roRead-only0x1APU core 0.