csu_ctrl (CSU) Register Description
| Register Name | csu_ctrl |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address | 0x00FFCA0004 (CSU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | CSU Control |
csu_ctrl (CSU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| slverr_enable | 4 | rwNormal read/write | 0x0 | Enable for the SLVERR signal during an address decode failure on the APB interface. 0: disable (default), invalid address requests are ignored and the system can hang. 1: enable, the SLVERR signal is asserted back to the master; writes are ignored and a read returns 0. |
| Reserved | 3:1 | rwNormal read/write | 0x0 | reserved |
| csu_clk_sel | 0 | rwNormal read/write | 0x0 | Selects the clock source for the CSU clock. This clock goes to the DMA, AES, SHA, & RSA. 0: SysOsc 1: PLL |