EDCIDSR (A53_DBG_1) Register Description
| Register Name | EDCIDSR |
|---|---|
| Offset Address | 0x00000000A4 |
| Absolute Address | 0x00FED100A4 (CORESIGHT_A53_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | External Debug Context ID Sample Register |
EDCIDSR (A53_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CONTEXTIDR | 31:0 | roRead-only | 0 | The sampled value of CONTEXTIDR_EL1, captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register, and EDCIDSR samples the current Banked copy of CONTEXTIDR. |