L3_TM_CALIB_DIG18 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

L3_TM_CALIB_DIG18 (SERDES) Register Description

Register NameL3_TM_CALIB_DIG18
Offset Address0x000000EC48
Absolute Address 0x00FD40EC48 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_CALIB_DIG18 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_CALIB_DIG18_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
PIPE_NSW_CODE_OR_2 7rwNormal read/write0x0Value generated by PCW.
PIPE_NSW_CODE_OR_1 6rwNormal read/write0x0Value generated by PCW.
PIPE_NSW_CODE_OR_0 5rwNormal read/write0x0Value generated by PCW.
TM_OR_PIPE_NSW_CODE 4rwNormal read/write0x0Value generated by PCW.
FORCE_EN_PIPE_NSW 3rwNormal read/write0x0Value generated by PCW.
TM_OR_EN_PIPE_NSW 2rwNormal read/write0x0Value generated by PCW.
USB2_CODE_OR_4 1rwNormal read/write0x0Value generated by PCW.
USB2_CODE_OR_3 0rwNormal read/write0x0Value generated by PCW.