PLC1 (SATA_AHCI_VENDOR) Register Description
| Register Name | PLC1 |
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| Offset Address | 0x0000000034 |
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| Absolute Address |
0x00FD0C00D4 (SATA_AHCI_VENDOR)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Port LinkCfg1 |
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Controls the configuration of the Link Layer for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
PLC1 (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Reserved | 31:7 | roRead-only | 0x0 | Reserved |
| CD | 6 | rwNormal read/write | 0x0 | Data Character or Primitive (CD): This bit specifies whether the data used during the primitive override should be a data character or a primitive. E.g. if CD = 1, Prim Override State = L_SendEOF and Override Primitive = WTRM, then a WTRM primitive will be inserted into the data stream instead of an EOF (whenever a rising edge is seen on Primitive Override Enable). If CD = 0, then a normal data character (as specified by Override Primitive) is inserted into the data stream instead of the EOF. |
| POS | 5:0 | rwNormal read/write | 0x0 | Primitive Override State (POS): These 6 bits are used in the Primitive Override Debug functionality. When the Link Layer detects a positive edge on Primitive Override Enable, it overrides the next primitive that would be inserted during the Prim Override State, with the data specified by the Override Primitive and CD configuration bits. |