GSBUSCFG0 (USB3_XHCI) Register Description
| Register Name | GSBUSCFG0 |
|---|---|
| Offset Address | 0x000000C100 |
| Absolute Address |
0x00FE20C100 (USB3_0_XHCI) 0x00FE30C100 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted. xHCI Register Power-On Value: The standard xHCI driver does not access this register. |
GSBUSCFG0 (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DATRDREQINFO | 31:28 | rwNormal read/write | 0 | DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM. |
| DESRDREQINFO | 27:24 | rwNormal read/write | 0 | DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo). Input to BUS-GM. |
| DATWRREQINFO | 23:20 | rwNormal read/write | 0 | DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo). Input to BUS-GM. |
| DESWRREQINFO | 19:16 | rwNormal read/write | 0 | DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM. |
| Reserved | 15:12 | roRead-only | 0x0 | Reserved for future use |
| DATBIGEND | 11 | rwNormal read/write | 0 | |
| DESBIGEND | 10 | rwNormal read/write | 0 | |
| Reserved | 9:8 | roRead-only | 0x0 | Reserved |
| INCR256BRSTENA | 7 | rwNormal read/write | 0 | INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 256-beat burst. |
| INCR128BRSTENA | 6 | rwNormal read/write | 0 | INCR128 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 128-beat burst. |
| INCR64BRSTENA | 5 | rwNormal read/write | 0 | INCR64 Burst Type Enable - Input to BUS-GM; For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 64-beat burst. |
| INCR32BRSTENA | 4 | rwNormal read/write | 0 | INCR32 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 32-beat burst. |
| INCR16BRSTENA | 3 | rwNormal read/write | 0 | INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 16-beat burst. |
| INCR8BRSTENA | 2 | rwNormal read/write | 0 | INCR8 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI master uses INCR to do the 8-beat burst. |
| INCR4BRSTENA | 1 | rwNormal read/write | 0 | INCR4 Burst Type Enable Input to BUS-GM; For the AXI configuration, when this bit is enabled the controller is allowed to do bursts of beat length 1, 2, 3, and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and writes from being broken up into separate transfers. |
| INCRBRSTENA | 0 | rwNormal read/write | 0 | Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4). 0: INCRX burst mode HBURST (for AHB configurations) and ARLEN/AWLEN (for AXI configurations) do not use INCR. They use only the following burst lengths: - 1 - 4 (if GSBUSCFG0.INCR4BrstEna = 1) - 8 (if GSBUSCFG0.INCR8BrstEna = 1) - 16 (if GSBUSCFG0.INCR16BrstEna = 1) - 32 (if GSBUSCFG0.INCR32BrstEna = 1) - 64 (if GSBUSCFG0.INCR64BrstEna = 1) - 128 (if GSBUSCFG0.INCR128BrstEna = 1) - 256 (if GSBUSCFG0.INCR256BrstEna = 1) 1: INCR (undefined length) burst mode - AHB configurations: HBURST uses SINGLE or INCR of any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256. - AXI configurations: ARLEN/AWLEN uses any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256. For cache line-aligned applications, this bit is typically set to 0 to ensure that the master interface uses only power-of-2 burst lengths (as enabled via GSBUSCFG0[7:0]). |