GPI3_ENABLE (PMU_LOCAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GPI3_ENABLE (PMU_LOCAL) Register Description

Register NameGPI3_ENABLE
Offset Address0x000000022C
Absolute Address 0x00FFD6022C (PMU_LOCAL)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable Events on PMU GPI3 Input Register.

Enable the propagation of events to the GPI3 interface of the PMU. GPI3 interrupt will be generated by all events that are enabled in this register.

GPI3_ENABLE (PMU_LOCAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PL_GPI31:0rwNormal read/write0x0GPI signals from PL.