ZDMA_CH_SRC_DSCR_WORD1 (ZDMA) Register Description
| Register Name | ZDMA_CH_SRC_DSCR_WORD1 |
|---|---|
| Offset Address | 0x000000012C |
| Absolute Address |
0x00FFA8012C (ADMA_CH0) 0x00FFA9012C (ADMA_CH1) 0x00FFAA012C (ADMA_CH2) 0x00FFAB012C (ADMA_CH3) 0x00FFAC012C (ADMA_CH4) 0x00FFAD012C (ADMA_CH5) 0x00FFAE012C (ADMA_CH6) 0x00FFAF012C (ADMA_CH7) 0x00FD50012C (GDMA_CH0) 0x00FD51012C (GDMA_CH1) 0x00FD52012C (GDMA_CH2) 0x00FD53012C (GDMA_CH3) 0x00FD54012C (GDMA_CH4) 0x00FD55012C (GDMA_CH5) 0x00FD56012C (GDMA_CH6) 0x00FD57012C (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | SRC DSCR Word 1 |
This register must remain stable while DMA Channel is enabled
ZDMA_CH_SRC_DSCR_WORD1 (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:17 | razRead as zero | 0x0 | Reserved for future use |
| MSB | 16:0 | rwNormal read/write | 0x0 | Upper 12-bits of Address |