APM0_RESULT22 (VCU_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

APM0_RESULT22 (VCU_SLCR) Register Description

Register NameAPM0_RESULT22
Offset Address0x0000000164
Absolute Address 0x00A0040164 (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x1FFF0000
DescriptionAPM0_RESULT22

APM0_RESULT22 (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
validity_check31roRead-only0x0This signal will toggle in alternate timing window. This is required for safe reading of accumulated read and write latencies parameters which requires more then one APM access. This bit field is read with all the latency related APB registers and this is expected to be same for all those registers.
Reserved30:29razRead as zero0x0reserved
min_wr_lat128:16roRead-only0x1FFF
Reserved15:13razRead as zero0x0reserved
max_wr_lat112:0roRead-only0x0