L3_TM_AUX_0 (SERDES) Register Description
| Register Name | L3_TM_AUX_0 |
|---|---|
| Offset Address | 0x000000D0CC |
| Absolute Address | 0x00FD40D0CC (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_TM_AUX_0 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_AUX_0_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| bit_0 | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_1 | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_2 | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_3 | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_4 | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_5 | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_6 | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bit_7 | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |