MIO_PIN_56 (IOU_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_56 (IOU_SLCR) Register Description

Register NameMIO_PIN_56
Offset Address0x00000000E0
Absolute Address 0x00FF1800E0 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 56 Multiplexer Controls.

MIO_PIN_56 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [56] input/output bank 2.
1: CAN1 TX output.
2: I2C1 SCL input/output clock.
3: FPD SWDT clock output.
4: SPI0 MISO input/output.
5: TTC3 clock input.
6: UART1 TxD output.
7: TracePort DQ[2] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: reserved
2: reserved
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: USB0 ULPI Data [0] input/output.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM2 RGMII Tx Data [3] output.
Reserved 0rwNormal read/write0x0reserved