SMMU_ITOP_PERF_INDEX (SMMU500) Register Description
| Register Name | SMMU_ITOP_PERF_INDEX |
|---|---|
| Offset Address | 0x000000200C |
| Absolute Address | 0x00FD80200C (SMMU_GPV) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Enables TBU performance interrupts. |
SMMU_ITOP_PERF_INDEX (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| WAY_IPA2PA_PF | 31:30 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| IPA2PA_PF_INDEX | 22:16 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| WAY_MTLB_WC | 15:14 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| MTLB_WC_INDEX | 11:0 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |