L2_TM_ANA_BYP_12 (SERDES) Register Description
| Register Name | L2_TM_ANA_BYP_12 |
|---|---|
| Offset Address | 0x000000902C |
| Absolute Address | 0x00FD40902C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L2_TM_ANA_BYP_12 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_ANA_BYP_12_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| uphy_PSO_HSRXDIG | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_PSO_HSRXDIG | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_PDN_HS_DES | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_PDN_HS_DES | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_RST_GF_MUX | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_RST_GF_MUX | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_ENABLE_CDR | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_ENABLE_CDR | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |