PP1_INT_RAWSTAT (GPU) Register Description
| Register Name | PP1_INT_RAWSTAT |
|---|---|
| Offset Address | 0x000000B020 |
| Absolute Address | 0x00FD4BB020 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Interrupt Rawstat Register |
PP1_INT_RAWSTAT (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:13 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| RESET_COMPLETED | 12 | rwNormal read/write | 0x0 | Whenever the pixel processor has been successfully reset, this interrupt source is set. |
| CALL_STACK_OVERFLOW | 11 | rwNormal read/write | 0x0 | The polygon list command call has been executed to many times recursively. It is treated as an end of list command and rendering stops. |
| CALL_STACK_UNDERFLOW | 10 | rwNormal read/write | 0x0 | The polygon list command return was executed without a call first. The return command is then treated as an end of list command and rendering stops. |
| INVALID_PLIST_COMMAND | 9 | rwNormal read/write | 0x0 | A command in the polygon list was invalid and rendering could not continue. The invalid command is treated as an end of list command. |
| WRITE_BOUNDARY_ERROR | 8 | rwNormal read/write | 0x0 | The pixel processor has attempted to write outside the write boundary set by the WRITE_BOUNDARY registers. The bus interface completes the previous bus transaction but does not initialize any new transactions before the WRITE_BOUNDARY is modified or disabled, or the renderer is reset. |
| CNT_1_LIMIT | 7 | rwNormal read/write | 0x0 | Performance counter PERF_CNT_1 has passed the limit set in PERF_CNT_1_LIMIT. The bus interface is stopped as with STOP_BUS, and this interrupt source set. The BUS_STOP interrupt is asserted when the bus is actually stopped. This is likely to occur after CNT_1_LIMIT has been triggered. |
| CNT_0_LIMIT | 6 | rwNormal read/write | 0x0 | Performance counter PERF_CNT_0 has passed the limit set in PERF_CNT_0_LIMIT. The bus interface is stopped as with STOP_BUS, and this interrupt source set. The BUS_STOP interrupt is asserted when the bus is actually stopped. This is likely to occur after CNT_0_LIMIT has been triggered. |
| BUS_STOP | 5 | rwNormal read/write | 0x0 | The renderer has been stopped by a STOP_BUS command. BUS_STOP is triggered only after the bus is actually stopped, making it likely that BUS_STOP is delayed a bit after CNT_x_LIMIT has been triggered. Operation can be continued by issuing the START_BUS command. |
| BUS_ERROR | 4 | rwNormal read/write | 0x0 | A bus transaction has ended with error. The pixel processor has been stopped and has to be reset before rendering can be started again. |
| FORCE_HANG | 3 | rwNormal read/write | 0x0 | The pixel processor has been forced into an illegal state by the FORCE_HANG command. The renderer must be reset before rendering can be started again. |
| HANG | 2 | rwNormal read/write | 0x0 | Watchdog timer limit reached. This state can also be triggered under normal rendering if you are running a shader where it is near to a never-ending inner loop. From the software perspective, you can ignore this state, because this is merely a hint from the HW that something might be wrong. The SW then decides to either reset the processor, or continue to let it run. |
| END_OF_TILE | 1 | rwNormal read/write | 0x0 | Rendering has been ended by an END_AFTER_TILE command. The framebuffer might be incomplete. |
| END_OF_FRAME | 0 | rwNormal read/write | 0x0 | Rendering has ended by completion of the polygon list. The framebuffer is complete. The interrupt is delayed until all outstanding write requests have completed. |