PPCS (SATA_AHCI_VENDOR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

PPCS (SATA_AHCI_VENDOR) Register Description

Register NamePPCS
Offset Address0x0000000048
Absolute Address 0x00FD0C00E8 (SATA_AHCI_VENDOR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0xF8000000
DescriptionPort Phy Status (PhyControlStatus).

Indicates the status of the Phy Control Layer for either Port 0 or Port 1. The Port monitored is controlled by the value programmed into the Port Config Register. Note: All Status Registers have no predefined Reset value. The value shown in reset is a typical value that will be read after reset but will be dependent on the SERDES status, the actual value read can differ from this.

PPCS (SATA_AHCI_VENDOR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PHYCE31:30roRead-only0x3Current 2 bit Code Error (PHYCE): snapshot within the Phy Control Layer
PHYDE29:28roRead-only0x3Current 2 bit Disparity Error (PHYDE): snapshot within the Phy Control Layer
PHYKC27roRead-only0x1Current 1 bit K Character (PHYKC): snapshot within the Phy Control Layer
PHYD26:11roRead-only0x0Current 16 bit Data (PHYD): snapshot within the Phy Control Layer
CCAC10wtcReadable, write a 1 to clear0x0Comma Alignment has changed (CCAC)
CCA 9:5roRead-only0x0Current Comma Alignment (CCA)
PCTRLS 4:0roRead-only0x0Phy Control State (PCTRLS)
0: HP0_HR_Start
1: HP1_HR_Reset
2: HP2_HR_AwaitCOMINIT
3: HP3_HR_Calibrate
4: HP4_HR_COMWAKE
5: HP5_HR_AwaitCOMWAKE
6: HP6_HR_AwaitAlign
7: HP7_HR_SendAlign
8: HP8_HR_Ready
9: HP9_HR_Partial
10: HP10_HR_Slumber
11: HP11_HR_AdjustSpeed
12: HP2B_HR_AwaitNoCOMINIT
13: HP5B_HR_AwaitNoCOMWAKE