ITC_CPU_IRQ_STA (VCU_DEC_TOP) Register Description
| Register Name | ITC_CPU_IRQ_STA |
|---|---|
| Offset Address | 0x000000910C |
| Absolute Address | 0x00A002910C (VCU_DECODE) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | CPU Interrupt Status |
ITC_CPU_IRQ_STA (VCU_DEC_TOP) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Return 0 when read |
| Extirq1InterruptStatus | 7 | roRead-only | 0x0 | EXTIRQ1 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Extirq0InterruptStatus | 6 | roRead-only | 0x0 | EXTIRQ0 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Rresp1InterruptStatus | 5 | roRead-only | 0x0 | RRESP1 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Bresp1InterruptStatus | 4 | roRead-only | 0x0 | BRESP1 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Rresp0InterruptStatus | 3 | roRead-only | 0x0 | RRESP0 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Bresp0InterruptStatus | 2 | roRead-only | 0x0 | BRESP0 interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |
| Reserved | 1 | razRead as zero | 0x0 | Return 0 when read |
| McuToCpuInterruptStatus | 0 | roRead-only | 0x0 | MCU-to-CPU interrupt status: 0: no interrupt / interrupt cleared 1: interrupt triggered |