PP1_MMU_ZAP_ONE_LINE (GPU) Register Description
| Register Name | PP1_MMU_ZAP_ONE_LINE |
|---|---|
| Offset Address | 0x0000005010 |
| Absolute Address | 0x00FD4B5010 (GPU) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | MMU Zap Cache Line Register |
PP1_MMU_ZAP_ONE_LINE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| MMU_ZAP_ONE_LINE | 31:0 | woWrite-only | 0x0 | Address to be invalidated from the page table cache |