L3_TM_IQ_ILL3 (SERDES) Register Description
Register Name | L3_TM_IQ_ILL3 |
---|---|
Offset Address | 0x000000D900 |
Absolute Address | 0x00FD40D900 (SERDES) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Register value is generated by Vivado PCW. |
L3_TM_IQ_ILL3 (SERDES) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TM_IQ_ILL3_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
ill_bypass_iq_calcode_f2 | 7:0 | rwNormal read/write | 0x0 | Value generated by PCW. |