PP1_WB2_TARGET_LAYOUT (GPU) Register Description
| Register Name | PP1_WB2_TARGET_LAYOUT |
|---|---|
| Offset Address | 0x000000A310 |
| Absolute Address | 0x00FD4BA310 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | WB2 Target Layout |
PP1_WB2_TARGET_LAYOUT (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| _ | 31:2 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| WB2_TARGET_LAYOUT | 1:0 | rwNormal read/write | 0x0 | 0 Linear layout. The pixels are stored in normal linear layout in memory. 1 Interleaved layout. This is a fully interleaved mode where pixels are stored in u-order in memory for best possible 2D locality. This normally requires a quadratic framebuffer with power of two sides, but can also be used if the width is twice the height and both sides are powers of two. 2 Interleaved blocks. Each 16x16 pixel block is interleaved u-order internally and then the blocks are stored linearly in the framebuffer. 3 Reserved = Undefined. |